Floating gate semiconductor nonvolatile memory cells, known as EEPROMS, for electrically erasable programmable read only memories, as well as EPROMs, for erasable programmable read only memories, were invented over 30 years ago. The devices allow charge storage on an electrically insulated, or floating, gate. The floating gate is not connected to any electrode, but is surrounded by dielectric material. Charge transfer occurs, in one type of operation, as programming voltages on other electrodes cause hot electrons or holes to penetrate surrounding insulation and become trapped on the gate. The logic state of the memory cell is determined by the presence or absence of charge on the floating gate which stores the charge until it is erased.
In U.S. Pat. No. 5,516,713, Hsue et al. teach a method of making EEPROM memory cells. A layer of silicon dioxide is grown over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. The silicon dioxide layer not covered by the patterned silicon nitride layer and the silicon nitride spacers is removed thereby exposing portions of the semiconductor substrate as tunneling windows. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer which is patterned to form a control gate. Passivation and metallization complete the fabrication of the NAND-type memory cell with improved coupling ratio.
One of the problems encountered in making devices even smaller is the limit of line widths, or feature widths, imposed by photolithography or beam lithography for any manufacturing process. In fact, every semiconductor manufacturing process has its own minimum feature size defined by its lithography equipment or processes. Over the years, the smallest line widths have become smaller and smaller, today being less than 100 nanometers. Yet it is possible to make transistors even smaller by means of clever processing, making features smaller than characteristic lithographic minimum feature sizes.
In U.S. Pat. No. 6,369,422, granted Apr. 9, 2002, to B. Lojek and assigned to the assignee of the present invention, there is disclosed a method of making a nonvolatile memory cell structure wherein the size of the thin oxide window remains finite, but the part of the oxide window through which charge is transferred may be reduced to a size smaller than the minimum feature size resolution of the lithography equipment being used. This is accomplished by positioning the fixed-size oxide window in such a manner that its size is limited and whose position controls the amount of charge allowed to be transferred through it. The oxide window is constructed such that a first part of it lays over only one part of the two opposing field oxide regions and its remaining part lies over the channel region of a MOS transistor, but does not extend across it. This effectively creates a slit and the size of the slit may be adjusted by moving the position of the oxide window. Parts of the oxide window constructed over the field oxide region cannot be used to allow charge transfer to the floating gate. Only the part of the oxide window that lies over the channel region may be used to permit such charge transfer. Thus, one can construct an effective charge transfer region that is quite small, i.e. smaller than the minimum feature size of lithography equipment. While small transistor size is possible with this construction, the small window becomes an area of concern because the tunneling oxide window must be protected from process steps that might erode oxide quality.
In U.S. patent application Ser. No. 10/143,225, filed May 9, 2002, now U.S. Pat. No. 6,624,027 granted Sep. 23, 2003, to E. Daemen, B. Lojek and A. Renninger and assigned to the assignee of the present invention, there is disclosed a nonvolatile transistor memory construction featuring a thin window having a length or width which is less than the minimum feature size of the fabrication process using lithography. A nitride mask over a gate oxide layer on a substrate is used to first create self-aligned source and drain regions for an EEPROM memory cell. The nitride mask protects the future channel which will exist between source and drain electrodes. After formation of source and drain, a second nitride layer is deposited in which nitride spacers are formed on either side of the nitride mask and etched to a desired dimension having a length whose length will be the dimension of the tunnel oxide. Gate oxide is removed on one side of the nitride mask so that the dummy spacer on this side can approach the substrate. This dummy spacer has no purpose except to define the length of the future tunnel oxide window. The size of the spacer is smaller than that which could be made by lithography, typically a fraction of one micron. A supplemental oxide deposition on the sides of the nitride forms an oxide nest with the nitride spacers within, in a sort of slot. When nitride is removed by an etching process, the nest is empty. The ability to etch a narrow nest or slot establishes the small dimension of the thin window to be formed in this space, rather than a reliance on photographic resolution in photolithography. Once the nitride spacer is removed, a layer of thin tunnel oxide is applied across the edge of the cell. Where two cells are simultaneously formed in symmetric relation, the thin oxide can extend past the edge of the cell, across the edge of an adjacent cell and into a region formerly occupied by a dummy spacer in the adjacent cell. Such a thin oxide stripe, extending across two cells, does not interfere with the formation of the remainder of the two cells. For example, poly-one is deposited across each cell and etched back to form a floating gate. Real nitride spacers may optionally be formed at edges of the poly one floating gate. Subsequent layers of oxide and poly-two complete the cell structure. It should be noted that the real nitride spacers are not in the same position as the former dummy spacers, which have been lost to etching. The optional real spacers remain in place, protecting edges of the poly-one floating gate from lateral mobile electron or ion migration into or out of the floating gate. Select transistors may be formed simultaneously with EEPROM structures using selected layers and steps, such as the implantation step for source and drain formation, an oxide deposition step following nitride removal. This oxide deposition forms a gate oxide for the select transistor but forms an inter-poly oxide for the EEPROM devices. The oxide deposition is followed by poly-two layer deposition. The select and EEPROM transistors are now finished in the usual way.
An object of the invention is to devise a compact construction for nonvolatile dual bit memory cell transistors without thin oxide tunneling layers.